Category "modelsim"

I wrote this code in Verilog and there are no error messages, but it doesn't work

This is the module: module test (output reg [7:0] Q_out, input [2:0] data_in); always begin case (data_in) 3'b000: Q_out = 8'b10000000;

Simulation Waveform in Intel Questas_fse/Quartus II doesn't update outputs

I'm attempting to run Quartus II ( Quartus Prime Version 21.1.0 Build 842 10/21/2021 Sj Lite Edition) on linux Pop OS 21.10. I fail to produce result on output

Verilog DUT System Verilog testbench: output to wire assignment 1s replaced with Xs

I have a Modelsim testbench in System Verilog testing a Verilog top-level module (ufm1) with another Verilog module (wishbone) used inside it, there's also a Sy

Verilog DUT System Verilog testbench: output to wire assignment 1s replaced with Xs

I have a Modelsim testbench in System Verilog testing a Verilog top-level module (ufm1) with another Verilog module (wishbone) used inside it, there's also a Sy