Category "riscv"

How does QEMU risc-v put FDT address in register a1?

From RISC-V OpenSBI's source code and documents, in OpenSBI firmware a1 preserves FDT address from the prior booting stage, which I guess is QEMU if the followi

Why are periperal registers 16 bit only on 32 bit MCUs such as STM32 and GD32VF103?

On 32 bit microcontrollers such as the ST STM32F103 (ARM core) or the GigaDevices GD32VF103 (RISC-V core) there are many registers for dealing with peripherals.

Understand EQU and >> operators on them in RISC-V assembly, with LUI and ADDI

my prof posted this as one of the answers to a homework problem. Can anyone break this down for me? I don't understand what he is doing with CON1 - CON4 and wha

Can CPU Out-of-Order-Execution cause memory reordering?

I know store buffer and invalidate queues are reasons that cause memory reordering. What I don't know is if Out-of-Order-Execution can cause memory reordering.

How to load an immediate number to a register in RV32I Base Instruction Set?

Recently, I am working on RV32I base instruction set, and I did not find any instruction looks like LD r1, imm. Thus, I am wondering how assembly programer load

RISC-V build 32-bit constants with LUI and ADDI

LUI (load upper immediate) is used to build 32-bit constants and uses the U-type format. LUI places the U-immediate value in the top 20 bits of the destinati

How to trace dynamic instruction in spike (on RISC-V)

I’m new for spike and RISC V. I’m trying to do some dynamic instruction trace with spike. These instructions are from a sample.c file. I have tried