module main(input A, B, C,button,clk100mhz,output [7:0]seg,[7:0]an); reg [3:0] D0; reg [3:0] D1; reg [3:0] D2; reg [7:0] Y; DISP7SEG m1 (clk
I am using a zed board with a Zynq 7000 on it. The end goal is to have the I2c-0 controller in the physical PS of the Zynq7000 to act as an I2c slave device. I
I am supposed to create 4 bit full adder verilog code in vivado.But when I try to test in the simulation.It give me z and x output.Which part of code I have to
In Vivado I succesfully made a simple blockdiagram to control the LEDs of my Zybo board. I can observe that the offset address for my LEDs is: 0x4120 0000 and t
I have a Verilog design from Xilinx that I am trying to understand. Coming from VHDL I have a hard time grasping the definitions inside the de