Use constants in VHDL and posterior synthesis

Question

In VHDL, I know about constants and variables, but at the moment I have only used the integer or std_logic_vector data types with them. In order to analyse and implement an Automatic gain control (AGC), I need to vary the alpha parameter. alpha value has 16 bits, so for example, if the selected value for alpha is 0.95, then in fixed point will be:

alpha = round(0.95 * (2 ^ (bits - 1))) = 31130

There is no problem in set the value in fixed point as:

signal alpha : std_logic_vector(15 downto 0) := "0111100110011010"; -- alpha = 31130

But, my first question is: is it possible set the value as a real value and, later, convert it to fixed point and set it into a variable : std_logic_vector?

The second question is: If the first question is realizable, then, the operations necessaries to convert the float value to fixed point, as the example below, are not synthesized, right?

The way that I thought in order to convert my real value to fixed point in VHDL is:

constant bits : integer := 16;

-- Real alpha value
constant r_alpha : real := 0.95;

-- Fixed point alpha value: this is the alpha that I'm going to use.
constant alpha : integer := r_alpha * (2 ** (bits - 1));

The example, obviously, doesn't work, and is presented in order to clarify my first question.