Category "fpga"

Generating number sequence in verilog (automat)

I was given a task to create verilog code that generates number sequence 323135343355. It should be generated like automat so it has states and next number in s

understand Finite state machine in a verilog

I am using an Artix 7 FPGA and writing my code in Xilinx ISE. I already have the Verilog code for the project I am working on. Unfortunately, I am not able to u

Simulation Waveform in Intel Questas_fse/Quartus II doesn't update outputs

I'm attempting to run Quartus II ( Quartus Prime Version 21.1.0 Build 842 10/21/2021 Sj Lite Edition) on linux Pop OS 21.10. I fail to produce result on output

VHDL wrapper for 1-wire core for DS18B20 temperature sensor

currently I am trying to write a VHDL wrapper for this Opencore Verilog module (1-wire master) so that I can send/receive from this temperature sensor (DS18B20)

VHDL 4-bit multiplier based on 4-bit adder

i am a bit new to VHDL and i try to learn by examples. So long story short i began with some basic examples like creating this Full Adder. entity FA is Port

Interface DHT22 to FPGA - elbert v2

Now i make a circuit to measure temperature and humidity, then display on LCD. This is my code for DHT22, i use Elbert V2. After genarating my project, it did

Use of Xil_Out32 in Xilinx SDK

In Vivado I succesfully made a simple blockdiagram to control the LEDs of my Zybo board. I can observe that the offset address for my LEDs is: 0x4120 0000 and t

Adding Library to VHDL Project

I am trying to use fixed point numbers in my VHDL project, but I keep having trouble implementing the library (found here http://www.eda-stds.org/fphdl/fixed_pk

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