Category "intel-fpga"

FPGA bitfile acting different with the simulation

I wrote some RTL like this: wire[255:0] tx_data; wire[4:0] tx_empty; reg [255:0] mask1, mask2, mask3; reg [95:0] tmp0, tmp1, tmp2, tmp3, tm

How to fix libXft.so.2: cannot open shared object file when simulating hardware in Quartus 20.1 running on Pop_OS 20.04

I have recently moved to Linux and am getting used to the OS, I managed to install and run Quartus 20.1 Lite and I was testing it out with an old working projec