Category "quartus"

I wrote this code in Verilog and there are no error messages, but it doesn't work

This is the module: module test (output reg [7:0] Q_out, input [2:0] data_in); always begin case (data_in) 3'b000: Q_out = 8'b10000000;

How to fix libXft.so.2: cannot open shared object file when simulating hardware in Quartus 20.1 running on Pop_OS 20.04

I have recently moved to Linux and am getting used to the OS, I managed to install and run Quartus 20.1 Lite and I was testing it out with an old working projec

Simulation Waveform in Intel Questas_fse/Quartus II doesn't update outputs

I'm attempting to run Quartus II ( Quartus Prime Version 21.1.0 Build 842 10/21/2021 Sj Lite Edition) on linux Pop OS 21.10. I fail to produce result on output