Category "system-verilog"

How can I use foreach and fork together to do something in parallel?

This question is not UVM specific but the example that I am working on is UVM related. I have an array of agents in my UVM environment and I would like to launc

How to write a module with variable number of ports in Verilog

I would like to write a module with a variable number of inputs, i.e. depending on some parameter, the result would be: module my_module #(LENGTH)( input c

System Verilog always_latch vs. always_ff

I am confused about the usage of statements always_ff and always_latch. The former would be used as: always_ff @ (posedge clk) begin a <= b; end while t

Verilog DUT System Verilog testbench: output to wire assignment 1s replaced with Xs

I have a Modelsim testbench in System Verilog testing a Verilog top-level module (ufm1) with another Verilog module (wishbone) used inside it, there's also a Sy

Verilog DUT System Verilog testbench: output to wire assignment 1s replaced with Xs

I have a Modelsim testbench in System Verilog testing a Verilog top-level module (ufm1) with another Verilog module (wishbone) used inside it, there's also a Sy