bit[2:0] size; bit[2:0] num; bit[59:0] data; data = 60'h12345; num = 3'h1; size = 3'h1; data = {(num+1){data[(size+1)*10-1:0]}}; ////Error-[IRIPS] Illegal
I wrote some RTL like this: wire[255:0] tx_data; wire[4:0] tx_empty; reg [255:0] mask1, mask2, mask3; reg [95:0] tmp0, tmp1, tmp2, tmp3, tm
This is the module: module test (output reg [7:0] Q_out, input [2:0] data_in); always begin case (data_in) 3'b000: Q_out = 8'b10000000;
This question is not UVM specific but the example that I am working on is UVM related. I have an array of agents in my UVM environment and I would like to launc
I would like to write a module with a variable number of inputs, i.e. depending on some parameter, the result would be: module my_module #(LENGTH)( input c
I am confused about the usage of statements always_ff and always_latch. The former would be used as: always_ff @ (posedge clk) begin a <= b; end while t
I have a Modelsim testbench in System Verilog testing a Verilog top-level module (ufm1) with another Verilog module (wishbone) used inside it, there's also a Sy
I have a Modelsim testbench in System Verilog testing a Verilog top-level module (ufm1) with another Verilog module (wishbone) used inside it, there's also a Sy