'functions in makefiles?

I have a slew of makefile targets that do the same thing:

${SOME_FILE}:
    ${FILES} | ${DIST_DIR}

    @@cat ${FILES} |                     \
        sed 's/@DATE/'"${DATE}"'/' |     \
        sed 's/@VERSION/'"${CR_VER}"'/'  \
        > ${OUT_FILE};

where ${FILES} and ${OUT_FILE} are the only things changing. I'm trying to figure out if it's possible to simplify these targets to something like:

${SOME_FILE}:
    compile(${FILES},${OUT_FILE})

Thanks for any insight.

makefile


Solution 1:[1]

GNU make has this:

To define a multi-line function, you would use this syntax:

Solution 2:[2]

If you don't want to restrict yourself to GNUmake, your best bet is probably to generate makefile fragments yourself and then include them.

Sources

This article follows the attribution requirements of Stack Overflow and is licensed under CC BY-SA 3.0.

Source: Stack Overflow

Solution Source
Solution 1 Jonathan Leffler
Solution 2 Jack Kelly

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