Category "intel"

Intel oneAPI dpcpp compiler with google test

I'm kinda new to the world of Intel's HPC toolchain and I'm facing some troubles making even simple DPC++ application to work when gtest is used as a testing fr

OneAPI installation Failed

I have Visual studio 2019 and 2022 installed with Intel OneAPI toolkit previously. It installed and worked flawlessly before. When I tried to install a newer ve

Why didn't x86 implement direct core-to-core messaging assembly/cpu instructions?

After serious development, CPUs gained many cores, gained distributed blocks of cores on multiple chiplets, numa systems, etc but still a piece of data has to p

Is it possible to popcount __m256i and store result in 8 32-bit words instead of the 4 64-bit using Wojciech Mula algorithm's?

I have recently discovered that AVX2 doesn't have a popcount for __m256i and the only way I found to do something similar is to follow the Wojciech Mula algori

Do UEFI DXE Drivers operate in real-mode? What about "ring -2" or "ring -3" code?

I asked a question referencing a mode sometimes referred to as ring -2 (System Management Mode) which can be exploited to create rootkits. There's also even a r

Correctly disable Hardware Prefetching with MSR in Skylake

I am trying to disable hardware prefetching on my machine: CPU family: 6 Model: 78 Model name: Intel(R) Core(TM) i5-6200U CPU

intel i225-v linux driver(ubuntu 20.04)

after kernel downgrade, every device drivers doesn't work. I want to download i225-v linux driver, and search this pagehttps://www.intel.co.kr/content/www/kr/ko

Why is XCHG reg, reg a 3 micro-op instruction on modern Intel architectures?

I'm doing micro-optimization on a performance critical part of my code and came across the sequence of instructions (in AT&T syntax): add %rax, %rbx mov %r

How to configure IOMMU protection for my hypervisor?

I'm developing my own bare-metal hypervisor over intel vt-x technology. My goal is to make it inaccessible to the OS I'm running over my hypervisor in any way,

Micro fusion and addressing modes

I have found something unexpected (to me) using the Intel® Architecture Code Analyzer (IACA). The following instruction using [base+index] addressing add

How to detect P/E-Core in Intel Alder Lake CPU?

Which logical processor belongs to the P-core group and which to E-core group? My first idea was to just check the base clock for each logical processor and the