Is it possible to execute all make commands that match a pattern?

Question

Suppose I define several make PHONY commands:

auto-build-foo
auto-build-bar
auto-build-biz
...
auto-build-inf

And I can observe them all with the following keystrokes in bash with autocompletion configured:

$: make auto-build-<tab><tab>
auto-build-foo
auto-build-bar
auto-build-biz
...
auto-build-inf

Then my natural unix instinct is to write:

make auto-build-*

To build them all.

---

I understand this sort of thing needs to be implemented in make as a feature, a makefile as some sort of rule system, or some custom shell that integrates bash-completion history with some make-specialized interpretation.

But it would cool and useful to get this "out-of-the-box".

Is there such a mechanism that is -- or will be -- in GNU make?

Answer 1

No, GNU Make command line argument do not support wildcard.

But, you can easily do the job in bash:

• One by one

$ for t in $(sed -e '/auto-build/!d' -e 's/:.*$//' -e 's/\n/ /' Makefile); do make "$t" ; done

• At once

$ my_targets=$(sed -e '/auto-build/!d' -e 's/:.*$//' -e 's/\n/ /' Makefile)

$ make "$my_targets"

From a Makefile perspective, if you create your own, an efficient way could be to encapsulate the targets in a variable each time you write them:

TARGET:=auto-build-foo
$(TARGET):
    @echo "$@"

ALL_TARGETS:=$(ALL_TARGETS) $(TARGET)

TARGET:=auto-build-bar
$(TARGET):
    @echo "$@"

ALL_TARGETS:=$(ALL_TARGETS) $(TARGET)

auto-all: $(ALL_TARGETS)

.PHONY: auto-all

will give:

$ make auto-all
auto-build-foo
auto-build-bar