understand Finite state machine in a verilog

Question

I am using an Artix 7 FPGA and writing my code in Xilinx ISE.

I already have the Verilog code for the project I am working on. Unfortunately, I am not able to understand this module- The full code is posted here.

My goal is to find out where these 6 states are defined in the FSM: Reset (000), Wait for password (010), Compare (100), Log in successful (110), Login failed (111), and Do operation (101) and change the encoding to 4 bits.

I don't understand how the FSM in the image is there in the code.

Is anyone generous enough to help, please? Can I get a description of what is being done here?

Answer 1

The posted code is not Verilog RTL (Register Transfer Level) source code. Rather, its a post synthesis Verilog netlist. It contains the vendors primitives, look up tables (LUTS, buffers, etc). There is no way to understand the correlation between the bubble diagram and a post synthesis netlist in code linked to, its machine generated by the FPGA build tool (ISE in this case).

To correlate the bubble diagram and code, locate the corresponding Verilog source code that was used to create the netlist.

You might be able to locate the source code like this: If you are on Linux, cd to near where the code is located and run

find . -iname '*.*v' | xargs grep 'Compare'

Here is an example of what a Verilog RTL state machine would look like:
https://www.asic-world.com/tidbits/verilog_fsm.html
The state variables and related logic are represented as parameter names (Verilog) or enumerations (in SystemVerilog). The state names are searchable using a text editor.