FPGA bitfile acting different with the simulation

Question

I wrote some RTL like this:

  wire[255:0] tx_data;   
    wire[4:0]   tx_empty;
    reg  [255:0] mask1, mask2, mask3;
    reg  [95:0] tmp0, tmp1, tmp2, tmp3, tmp4;
    wire [95:0] timestamp, timestamp_xq;
    register_reset #(96)  ts_xq_reg (timestamp_xq, timestamp, clock, reset);
    assign timestamp =  (tx_eop & tx_valid)? ((tx_empty < 5'd17)? tmp0 : ((tx_empty < 5'd28) ? tmp3  : tmp4)) :  timestamp_xq ;
    always_comb begin
            tmp0 = '0;
            tmp1 = '0;
            tmp2 = '0;
            tmp3 = '0;
            tmp4 = '0;
            mask1 = '0;
            mask2 = '0;
        if(tx_eop & tx_valid)begin   
            if (5'd27 <tx_empty && (tx_empty <= 5'd31))begin   //index 28-31
                tmp4 = tx_data[(tx_empty - 5'd28)*8 +: 96];
                end
            else if (5'd16<tx_empty && tx_empty<5'd28) begin//index 17-27
                mask1 = (256'b1 << (tx_empty - 5'd16)*8) - 1;
                tmp1 = (tx_data & mask1) << ((5'd28 - tx_empty)*8);
                mask2 = ~((256'b1 << (tx_empty+5'd4)*8) - 1) ;
                tmp2 = (tx_data & mask2) >> (tx_empty+5'd4)*8;
                tmp3 = tmp1 | tmp2;
                end    
            else begin //0-16
                tmp0 = tx_data[(tx_empty + 5'd4)*8 +: 96];
                end 
        end
    end

tmp0 should only change when tx_data and tx_empty changes, and it works fine in the simulation:

But after I generated the bitifile and used the signalTap, the value of tmp0 is weird. It doesn't make any sense to me why the tmp0 is not equal to 16BAD...4CCAh when the tx_eop && tx_valid is 1 and tx_empty is 12. tmp0 should equal to tx_data[16*8 +: 96] in this case.

Also the value of timestamp is weird, I don't know where it is from. I have checked the latch report and timing report in quartus, no latch inferred and no timing violation.

WAVEFORM USING JTAG

Thx in adv