VHDL Counter mod 60

Question

I need help with this counter mod 60. Please help !
The T60 is the signal when count hit 59, 0 or 1 if is the case. Also when count hit 60, countget reseted to "000000".
When RESET60 is '1', count get "000000". EN60 is not in use, for now.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity counter60 is
    port(   CLK:    in std_logic;
            EN60:   in std_logic;
            RESET60: in std_logic;
            T60:    out std_logic); 
end entity;

architecture sim of counter60 is
signal count: std_logic_vector(0 to 5);
begin
    T60 <= '0';
    process(CLK,RESET60)
    begin
        if(RESET60 = '1') then
            count <= "000000";
        elsif (CLK'EVENT and CLK = '1')
            then count <= count + 1;
        end if;
        
        if(count <= "111100") then 
            count <= "000000";
        end if;
        
        if(count <= "111011") then
            T60 <= '1';
        else
            T60 <= '0';
        end if;
        
    end process;
end architecture;

Answer 1

I highly recommend not using IEEE.STD_LOGIC_ARITH or IEEE.STD_LOGIC_UNSIGNED. They are not standard VHDL. A better option is to use the standard IEEE.NUMERIC_STD package.

Then you want something like this:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;

entity counter60 is
    port(   CLK:    in std_logic;
            RESET60: in std_logic;
            T60:    out std_logic); 
end entity;

architecture sim of counter60 is
    signal count : unsigned(5 downto 0);
begin
    
    process(CLK, RESET60)
    begin
        if (RESET60 = '1') then
            T60 <= '0';
            count <= (others => '0');
        elsif (CLK'EVENT and CLK = '1') then
            if count < 59 then
                T60 <= '0';
                count <= count + 1;
            else
                T60 <= '1';
                count <= (others => '0');
            end if;
        end if;
    end process;

end architecture;

Explanation

T60 is assigned to '0' for 59 clock cycles as the counter counts from 0 to 58. Then T60 is set to '1' for one clock cycle after the counter reaches 59 (after which, the counter is reset to 0).