code for clock generation in structural verilog

Question

I was trying to teach myself verilog programming from "The Verilog HDL" book by Thomas Moorby. In one of the exercises, they asked to generate a clock using structural verilog only (except for the $monitor part of course).

I tried the following:

module clock();
    wor clk;
    assign clk=0;

    initial begin 
        $monitor($time,,"clk=%b", clk);
        #100 $finish;
    end

    assign #5 clk = ~clk;
endmodule

Problem is, it works in iVerilog 0.9.7, but for version 10.0 and above, it does not work.. I simply get undefined value for clk!

Does not seem like a bug in iVerilog, otherwise it would probably have been fixed in one of the 10.x releases. Is there any other way to get this working? Also, what is wrong with the current code (if any) ?

Answer 1

this is a messy code you have. usually clock generation done with regs as one of the following

reg clk;
initial begin
    clk = 0;
    forever 
         #5 clk = ~clk;
end

or

 always 
     #5 clk = ~clk;
 initial 
     clk = 0;

Answer 2

Strange code, you are resolving clk drives using an or-gate behaviour. First assign is constantly driving 0. Second assign is inverting the resolved value. But what is the initial value of the second wor input? Wouldn't that second assign produce X in the first place (X ored with 0 would give you X)? Have your tried running it in the simulator or at least drawing somewhere what hardware do you want to get? It's like you're feeding and inverter with 0 or'ed with X which will produce X.

If you want to model a clock you can:

1) convert first assign into initial begin clk = 0; end

2) second assign to always

3) make clk reg type

If you want a synthesizable clock generator you would require a source of oscillations, PLL, etc.