'how can i take slice from a fifo buffer?
I write a code for asynchronous fifo ,here i am taking 32 bit write data and at write clock and getting a output at read clock . Here i am using 32 bit ASM(32'h1ACFFC1D) as marker . now I want a slicer of length of 501 bits (slicer_lemgth [500:0]). How can I get a reg of 501 bits from thse data bits . The code written by me is given below . please help me out from this problem . any suggestion is highly appriciated.
As you can see in image slicer output is of some k digit(501 bits) and the SMTF is data from fifo . For this slicer_length can I take data bits from fifo buffer ? or by read data values from fifo , i am not sure about that
module asy_fifo(wr_clk,wr_rst,wr_en,wr_data,full,rd_clk,rd_rst,rd_en,rd_data,empty,slicer_length,sync_marker);
parameter DATA_WIDTH = 32;
parameter DATA_DEPTH = 10;
parameter [31:0]ASM = 32'h1ACFFC1D;
parameter slicer_k ='d10046;
input wr_clk;
input wr_rst;
input wr_en;
input [DATA_WIDTH - 1 : 0] wr_data;
output reg full;
input rd_clk;
input rd_rst;
input rd_en;
output reg [DATA_WIDTH - 1 : 0] rd_data;
output reg empty;
output reg[500:0] slicer_length;
reg[7:0] count
integer i;
// define FIFO buffer
reg [DATA_WIDTH - 1 : 0] fifo_buffer[0 : DATA_DEPTH - 1];
//define the write and read pointer and
//pay attention to the size of pointer which should be greater one to normal
reg [$clog2(DATA_DEPTH) : 0] wr_pointer = 0, rd_pointer = 0;
//write data to fifo buffer and wr_pointer control
always@(posedge wr_clk ) begin
if(wr_rst==1|| count==8 ) begin
wr_pointer <= 0;
count =0;
end
else if(wr_en) begin
count = count+1;
wr_pointer <= wr_pointer+1;
//fifo_buffer[wr_pointer] <= A;
end
end
always@(posedge wr_clk )
begin
if (wr_rst)
fifo_buffer[wr_pointer] <=0;
else if (wr_en)
fifo_buffer[wr_pointer] <= A;
end
always@(posedge wr_clk)
begin
if (count==0)
A <= ASM;
else if(count>0)
A <= wr_data;
end
//read data from fifo buffer and rd_pointer control
always@(posedge rd_clk) begin
if(rd_rst)
begin
rd_pointer <= 0;
end
else if(rd_en) begin
rd_pointer <= rd_pointer+1;
rd_data <= fifo_buffer[rd_pointer];
end
end
//wr_pointer and rd_pointer translate into gray code
wire [$clog2(DATA_DEPTH) : 0] wr_ptr_g, rd_ptr_g;
assign wr_ptr_g = wr_pointer ^ (wr_pointer >>> 1);
assign rd_ptr_g = rd_pointer ^ (rd_pointer >>> 1);
//wr_pointer after gray coding synchronize into read clock region
reg [$clog2(DATA_DEPTH) : 0] wr_ptr_gr, wr_ptr_grr, rd_ptr_gr, rd_ptr_grr;
always@(rd_clk) begin
if(rd_rst) begin
wr_ptr_gr <= 0;
wr_ptr_grr <= 0;
end
else begin
wr_ptr_gr <= wr_ptr_g;
wr_ptr_grr <= wr_ptr_gr;
end
end
//rd_pointer after gray coding synchronize into write clock region
always@(wr_clk) begin
if(wr_rst) begin
rd_ptr_gr <= 0;
rd_ptr_grr <= 0;
end
else begin
rd_ptr_gr <= rd_ptr_g;
rd_ptr_grr <= rd_ptr_gr;
end
end
// judge full or empty
always@(posedge rd_clk) begin
if(rd_rst) empty <= 0;
else if(wr_ptr_grr == rd_ptr_g) begin
empty <= 1;
end
else empty <= 0;
end
always@(posedge wr_clk) begin
if(wr_rst) full <= 0;
else if( (rd_ptr_grr[$clog2(DATA_DEPTH) - 1 : 0] == wr_ptr_g[$clog2(DATA_DEPTH) - 1 : 0])
&& ( rd_ptr_grr[$clog2(DATA_DEPTH)] != wr_ptr_g[$clog2(DATA_DEPTH)] ) ) begin
full <= 1;
end
else full <= 0;
end
endmodule
Testbench
module asy_fifo_tb();
parameter DATA_WIDTH = 32;
parameter DATA_DEPTH = 10;
reg wr_clk;
reg wr_rst;
reg wr_en;
reg [DATA_WIDTH - 1 : 0] wr_data;
wire full;
reg rd_clk;
reg rd_rst;
reg rd_en;
wire [DATA_WIDTH - 1 : 0] rd_data;
wire empty;
wire [63:0] sync_marker;
wire slicer_length;
// reg [11:0]count;
initial begin
wr_clk = 0;
forever begin
#5 wr_clk = ~wr_clk;
end
end
initial begin
rd_clk = 0;
forever begin
#10 rd_clk = ~rd_clk;
end
end
initial begin
$monitor("wr_data=%b,re_data=%b,empty=%b,full=%b,count=%d,fifo_buffer=%b,slicer_length=%b",wr_data,rd_data,empty,full,dut.count,dut.rd_pointer,slicer_length);
wr_rst = 1;
rd_rst = 1;
wr_en = 0;
rd_en = 0;
#30
wr_rst = 0;
rd_rst = 0;
//write data into fifo buffer
@(negedge wr_clk)
wr_data = $random;
wr_en = 1;
repeat(8) begin
@(negedge wr_clk)
wr_data = $random; // write into fifo 8 datas in all;
end
// read parts
@(negedge wr_clk)
wr_en = 0;
@(negedge rd_clk)
rd_en = 1;
repeat(8) begin
@(negedge rd_clk); // read empty
end
@(negedge rd_clk)
rd_en = 0;
//write full
# 150
@(negedge wr_clk)
wr_en = 1;
wr_data = $random;
repeat(7) begin
@(negedge wr_clk)
wr_data = $random;
end
@(negedge wr_clk)
wr_en = 0;
@(negedge rd_clk)
rd_en =1;
repeat(7) begin
@(negedge rd_clk);
end
//@(negedge rd_clk)
// rd_en=0;
#150
@(negedge wr_clk)
wr_en = 1;
wr_data = $random;
repeat(7) begin
@(negedge wr_clk)
wr_data = $random;
end
//#50 $finish;
end
asy_fifo dut(
//.DATA_WIDTH(DATA_WIDTH),
//.DATA_DEPTH(DATA_DEPTH),
//) inst_asy_fifo (
.wr_clk (wr_clk),
.wr_rst (wr_rst),
.wr_en (wr_en),
.wr_data (wr_data),
.full (full),
.rd_clk (rd_clk),
.rd_rst (rd_rst),
.rd_en (rd_en),
.rd_data (rd_data),
.empty (empty),
.slicer_length(slicer_length),
.sync_marker(sync_marker)
);
endmodule
Sources
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Source: Stack Overflow
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