'Understanding Verilog signal width parameter inheritance [duplicate]

I have a Verilog design from Xilinx that I am trying to understand. Coming from VHDL I have a hard time grasping the definitions inside the design. Things are written as though they should be explicit. But as soon as I run the simulation things are completely different.

As in the example in the image below: Inside the entity block, there is a parameter STRB_WIDTH = 2. So I am expecting the output signal AXI4_S_OP_TKEEP [0:(STRB_WIDTH-1)] to have a 2 bit width. The simulation on the right however shows a 32 bit length.

edit: solved by @toolic by pointing to the instantiation

// Frame Checker to check output from RX_Stream
aurora_64b66b_0_FRAME_CHECK #
    (
    .DATA_WIDTH(256),
    .STRB_WIDTH(32)
    )
    frame_check_i
    (
    // AXI4-S input signals
    .AXI4_S_IP_TX_TVALID(rx_tvalid_i),
    .AXI4_S_IP_TX_TREADY(),
    .AXI4_S_IP_TX_TDATA(rx_tdata_i),
    .AXI4_S_IP_TX_TKEEP(rx_tkeep_i),
    .AXI4_S_IP_TX_TLAST(rx_tlast_i),
    .DATA_ERR_COUNT(data_err_count_o),

    .CHANNEL_UP(channel_up_i),
    .USER_CLK(user_clk_i),
    .RESET(reset2FrameCheck)
    );

Screenshot of Xilinx Vivado

verilog xilinx

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'Understanding Verilog signal width parameter inheritance [duplicate]

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