Signal assignments from multiple if statements

Question

Out of academic interest, is the following code acceptable:

logic a, b, c;
int out;
always_ff @(posedge clk) begin
  out <= 1;
  if (a) out <= 2;
  if (b) out <= 3;
  if (c) out <= 3;
end

Inside always-block things should be sequential, right? So, in this example by default out would be 1 but a, b and c could override the value in "prioritized" order.

Or is there a risk of unknown result in synthesis? I.e. the order of assignments would be random like this:

  if (c) out <= 3;
  out <= 1;
  if (b) out <= 3;
  if (a) out <= 2;

In this case, even if c was 1 out would be 1 (or something else if a or b are 1).

Answer 1

When you have code inside a begin/end block, the statements are guaranteed to execute in serial order. And with non-blocking assignment, the result is predictable when the statement order is predictable. So you get the prioritized order you are expecting.